1. Field of Invention
The present invention relates to a data communication method and, in particular, to serial data communication for a television device, a video device, a DVD recorder device, an audio device, or the like.
2. Prior Art
In the prior art, methods of controlling data transfer are known in which a controlling semiconductor apparatus and a plurality of to-be-controlled semiconductor apparatuses are interconnected using two or three transmission lines. Among such techniques, the Philips INTER-IC (I2C) bus is described below.
An I2C bus is shown in FIG. 6. As shown in FIG. 6, in the I2C bus, a controlling semiconductor apparatus (referred to as a “master”, hereinafter) 1 and a plurality of to-be-controlled semiconductor apparatuses (each referred to as a “slave”, hereinafter) 4 are interconnected using two transmission lines 2 and 3. The master 1 controls each slave 4 via the transmission lines 2 and 3.
The master 1 is an apparatus that starts data transfer, then generates a clock signal, and then completes the data transfer. Each slave 4 is an apparatus addressed by the master 1. One of the two transmission lines is a line (referred to as a “serial clock line”, hereinafter) 2 for transmitting the clock signal. This signal is transmitted by the master 1 and received by each slave 4. The other is a line (referred to as a “serial data line”, hereinafter) 3 for transmitting data between the master 1 and each slave 4. This line is used for data transmission in order that the master 1 should control each slave 4. Then, the master 1 transmits data to each slave 4 by serial transmission.
A unique address (referred to as a “slave address”, hereinafter) is provided to each slave 4. When controlling each slave 4, the master 1 first transmits to the serial data line 3 the slave address of the slave 4 to be controlled. Only when having received own slave address, each slave 4 receives data that follows the slave data. As such, since a unique address is provided to each slave 4, the serial clock line 2 and the serial data line 3 can be shared by these slaves 4.
Further, in the I2C bus, in response to an instruction from the master 1, the data held by each slave 4 can also be transmitted to the master 1 via the serial data line 3. The data transmission is performed in predetermined order. When no instruction is provided from the master 1, the data held by each slave 4 cannot be transmitted to the master 1. That is, complete two-way communication is not established between the master 1 and each slave 4.
Next, an example of a system employing the above-mentioned I2C bus is described below. FIG. 7 is a diagram showing a configuration of a communication system employing an I2C bus shown in FIG. 6.
First, the operation is described that the master 1 writes data into the slave 4. In FIG. 7, the master 1 performs serial conversion on transmission data 5 by using a serial converter 6, and then transmits the converted data to the serial data line 3. The transmission data 5 consists of: slave address data (7 bits) of the slave 4; data write/read select data (1 bit) for the slave 4; and data for controlling the slave 4. The data write/read select data indicates that the data is written from the master 1 into the slave 4. The transmission data 5 is processed by serial conversion in the order of the slave address data, the data write/read select data, and the slave control data.
The slave 4 receives the data 5 transmitted from the master 1 to the serial data line 3. The received data 5 is processed by parallel conversion in a parallel converter 7, and then stored into a received data memory 8. The control data in the stored data 5 is transmitted to various kinds of function control sections 9 in the slave 4 so that the slave 4 is controlled on the basis of this data. Then, the operation is completed that the master 1 writes data into the slave 4.
Next, the operation is described that the master 1 reads data stored in the slave 4. Similarly to the above-mentioned write operation, the master 1 performs serial conversion on transmission data 5 by using the serial converter 6, and then transmits the converted data to the serial data line 3. The transmission data 5 consists of slave address data (7 bits) of the slave 4 and data write/read select data (1 bit) for the slave 4. Here, the data write/read select data indicates that the master 1 reads data from the slave 4. The transmission data 5 is processed by serial conversion in the order of the slave address data and the select data.
The slave 4 receives the data 5 transmitted from the master 1 to the serial data line 3. This data is processed by parallel conversion in the parallel converter 7, and then stored into the received data memory 8. The select data in the transmission data 5 is transmitted from the memory 8 through the read instruction signal line 10 to a serial converter 11. In accordance with the select data that indicates data read, the slave 4 performs serial conversion on system information data 12 in the slave 4 by using the serial converter 11, and then transmits the converted data to the serial data line 3.
The master 1 receives the data 12 transmitted to the serial data line 3, then performs parallel conversion on the received data by using the parallel converter 13, and then stores the converted data into a received data memory 14. Then, the operation is completed that the master 1 reads data stored in the slave 4.
As such, in the system of FIG. 7, the master 1 can write data into the slave 4 and read data from the slave 4.
As for prior art document information concerning the present invention, for example, Non-Patent Document 1 is known
Non-Patent Document 1: “The I2C-bus specification” http://www.semiconductors.philips.com/acrobat_download/lite rature/9398/39340011.pdf
FIG. 8 shows an example of a data map of the system information data 12 of FIG. 7. This shows a case that the system information data 12 consists of 128 pieces of data. In FIG. 8, serial conversion order for the data 12 is set up in advance into the order from MSB to LSB and from sub-address 0 to sub-address F. In this case, the data 12 is processed by serial conversion in the order of the numerical values assigned in the grid sections of FIG. 8. For example, the data of sub-address E and address 7 is processed by serial conversion in the 113th turn, and then transmitted to the serial data line 3.
Nevertheless, in the system shown in FIG. 7, the read of the system information data 12 of the slave 4 has been performed by serial transmission. Thus, data processed in a later turn of serial conversion takes a longer time to be received by the master 1. That is, data having a larger numerical value in the grid section of FIG. 8 takes a longer time to be received by the master 1. This problem need be resolved in the situation that the amount of data transmitted from the slave 4 increases with increasing scale and increasing functional complexity in semiconductor apparatuses in recent years.
Further, even when the data transmitted from the serial converter 11 at the last is solely necessary, the master 1 need read the entire data of the system information data 12. Thus, the master 1 need be provided with a receiving memory 14 capable of holding the entire data of the slave 4. This unavoidably causes a size increase in the memory 14.